Power consumption is an issue for advanced integrated circuit parts such as transistors. Tunneling leakage current (gate leakage) and standby leakage current (source drain leakage) contribute to the power consumption problem.
One approach used in the past to address tunneling leakage currents in transistors was to fabricate the transistors with a thicker gate dielectric. This approach, however, had several drawbacks. First, fabricating a transistor with a thicker gate dielectric involved multiple gate oxidations. This required additional time and resources for implementing additional processes during manufacturing which was undesirable. Second, although fabricating the transistor with a thicker gate dielectric reduced the tunneling leakage current when the transistor was in an ON state, the approach did not address the standby leakage current when the transistor was in an OFF state. On the contrary, fabricating the transistor with a thicker gate dielectric increased the amount of standby leakage current generated between the source and drain which was undesirable.
Thus, what is needed is an efficient and effective approach to addressing both tunneling leakage current and standby leakage current.